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the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. ? 2001 mos integrated circuit mc-2311100 mcp (multi-chip package) mobile specified ram and sram 16m-bit cmos mobile specified ram and 4m-bit cmos sram preliminary data sheet document no. m15432ej1v0ds00 (1st edition) date published november 2001 ns cp (k) printed in japan the mark shows major revised points. description the mc-2311100 is a stacked type mcp (multi-chip package) of 16,777,216 bits (1,048,576 words by 16 bits) mobile specified ram and 4,194,304 bits (byte mode : 524,288 words by 8 bits, word mode : 262,144 words by 16 bits) sram. the mc-2311100 is packaged in a 61-pin tape fbga. general features ? supply voltage : v cc m / v cc s = 2.6 to 3.0 v ? wide operating temperature : t a = ? 20 to +70 c ? output enable input for easy application ? byte data control : /lb (i/o0 to i/o7), /ub (i/o8 to i/o15) mobile specified ram features ? memory organization : 1,048,576 words by 16 bits ? fast access time : t aa = 80, 90, 100 ns (max.) ? supply current : at operating : 35 ma (max.) at standby mode 1 : 100 a (max.) normal standby (memory cell data hold valid) at standby mode 2 : 10 a (max.) memory cell data hold invalid ? chip enable inputs : /cem ? standby mode input : mode sram features ? memory organization : 524,288 words 8 bits (byte mode) 262,144 words 16 bits (word mode) ? fast access time : t aa = 70 ns (max.) ? supply current : at operating : 40 ma (max.) at standby mode : 7 a (max.) ? low v cc data retention: 1.0 v (min.) ? two chip enable inputs: /ce1s, ce2s
preliminary data sheet m15432ej1v0ds 2 mc-2311100 ordering information part number access time ns (max.) package mobile specified ram sram mc-2311100f9-b80-bq1 80 70 61-pin tape fbga (9 7) MC-2311100F9-B90-BQ1 note 90 70 mc-2311100f9-b10-bq1 100 70 note under development
preliminary data sheet m15432ej1v0ds 3 mc-2311100 pin configuration /xxx indicates active low si gnal. 61-pin tape fbga (9 7) top view top view bottom view 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 a bcdefghj k nc nc nc nc nc v ss a17 sa a16 i/o6 i/o1 a1 a4 a10 a0 a14 v ss a7 a11 a8 /we /lb nc i/o8 i/o14 i/o5 cios i/o2 i/o11 a6 ce2 a12 a15 a19 a3 mode /ub i/o0 v cc s i/o7 v ss i/o12 /cem v cc m i/o10 a18 a5 a13 nc a9 a2 nc nc i/o9 /oe i/o15 i/o3 i/o13 /ce1s i/o4 nc abcdefghjk kjhgfedcba common pins a0 - a19 : address inputs i/o0 - i/o15 : data inputs / outputs /oe : output enable /we : write enable /lb, /ub : byte data select v ss : ground nc note : no connection mobile specified ram pins /cem : chip enable mode : standby mode select v cc m : supply voltage sram pins /ce1s : chip enable ce2s : chip enable sa : address input (a18) cios : selects 8-bit or 16-bit mode v cc s : supply voltage note some signals can be applied because this pin is not internally connected. remark refer to 5. package drawing for the index mark.
preliminary data sheet m15432ej1v0ds 4 mc-2311100 block diagram /ce 1s i/o0 - i/o15 4 m-bit sram 524,288 words by 8 bits 262,144 words by 16 bits /lb /ub /we /oe v cc s v ss /cem mode ce 2s sa(a18) cio s 16 m-bit mobile specified ram (1,048,576 words by 16 bits) v cc m v ss a0 - a19 a0 - a19 a0 - a17
preliminary data sheet m15432ej1v0ds 5 mc-2311100 contents 1. bus operations ............................................................................................................... ....................................6 2. mobile specified ram ......................................................................................................... ................................7 2.1 initialization.............................................................................................................. ...................................7 2.2 standby mode ................................................................................................................ .............................8 2.2.1 standby mode state machine ................................................................................................ ................8 3. electrical specifications.................................................................................................... .................................9 4. timing charts ................................................................................................................ ....................................19 5. package drawing .............................................................................................................. ................................42 6. recommended soldering conditions ............................................................................................. ................43
preliminary data sheet m15432ej1v0ds 6 mc-2311100 1. bus operations table 1-1. bus operations operation mobile specified ram sram common /cs mode /ce1 ce2 cios /oe /we /lb /ub i/o0 to i/o7 i/o8 to i/o15 full standby standby mode1 h h h x xxxxx hi-z hi-z xl standby mode2 l h x xl output disable l h l h x h h x x mobile specified ram /cs mode /ce1 ce2 cios /oe /we /lb /ub i/o0 to i/o7 i/o8 to i/o15 word read (1m x 16) l h note1 xlhll d out d out lower byte read l h d out hi-z upper byte read h l hi-z dout output disable h h hi-z hi-z word write (1m x 16) x l l l d in d in lower byte write l h d in hi-z upper byte write h l hi-z d in write impossible h h hi-z hi-z sram /cs mode /ce1 ce2 cios /oe /we /lb /ub i/o0 to i/o7 i/o8 to i/o15 byte read (512k x 8) note2 lhllhl l d out hi-z word read (256k x 16) h l l d out d out lower byte read l h d out hi-z upper byte read h l hi-z d out output disable l h x x x x x h h hi-z hi-z byte write (512k x 8) note2 lhl x ll l d in hi-z word write (256k x 16) h l l d in d in lower byte write l h d in hi-z upper byte write h l hi-z d in caution other operations except for indicated in this table are inhibited. notes 1. sram should be standby. 2. mobile specified ram should be standby. remarks 1. h : v ih , l : v il , : v ih or v il 2. mode pin must be fixed to h during active operation.
preliminary data sheet m15432ej1v0ds 7 mc-2311100 2. mobile specified ram 2.1 initialization the mc-2311100 is initialized in the power-on sequence according to the following. (1) to stabilize internal circuits, before turning on the power, a 200 s or longer wait time must precede any signal toggling. (2) after the wait time, read operation must be performed at least 8 times. after that, it can be normal operation. figure 2-1. initialization timing chart address (input) /cem (input) v cc m v cc m (min.) v ih (min.) v ih (min.) mode (input) t rc t cp wait time power on read operation 8 times normal operation 200 s cautions 1. following power application, make mode and /cem high level during the wait time interval. 2. following power application, make mode high level during the wait time and eight read operations. 3. the read operation must satisfy the specs described on page 14 (read cycle (mobile specified ram)). 4. the address is don?t care (v ih or v il ) during read operation. 5. read operation must be executed with toggled the /cem pin. 6. to prevent bus contention, it is recommended to set /oe to high level. however, do not input data to the i/o pins if /oe is low level during a read operation.
preliminary data sheet m15432ej1v0ds 8 mc-2311100 2.2 standby mode standby mode 1 and standby mode 2 differ as shown below. table 2-1. standby mode characteristics standby mode memory cell data hold standby supply current ( a) mode 1 valid 100 (i sb1 ) mode 2 invalid 10 (i sb2 ) 2.2.1 standby mode state machine (1) from active to shift from this state to standby mode 1, change /cem from v il to v ih . to shift from this state to standby mode 2, change /cem from v il to v ih and change mode from v ih to v il . (2) from standby mode 1 to shift from this state to active, change /cem from v ih to v il . to shift from this state to standby mode 2, change mode from v ih to v il . (3) from standby mode 2 when shifting from this state to the active state or to standby mode 1, it is necessary to set mode to v ih and perform a dummy read operation 8 times after waiting for 200 s, in the same way as at power application. refer to figure 4-16. standby mode 2 entry and recovery timing chart (mobile specified ram) . after shifting to active state, change /cem to v il . after shifting to standby mode 1, do not change either mode or /cem. figure 2-2. standby mode state machine /cem = v ih , mode = v ih mode = v ih /cem = v ih , mode = v ih /cem = v ih , mode = v il /cem = v ih , mode = v il /cem = v il , mode = v ih /cem = v ih , mode = v ih /cem = v il wait 200 s, dummy read (8 times) power on initial state active standby mode 1 standby mode 2
preliminary data sheet m15432ej1v0ds 9 mc-2311100 3. electrical specifications absolute maximum ratings parameter symbol condition rating unit supply voltage v cc m with respect to v ss ?0.5 note to +4.0 v v cc s with respect to v ss ?0.5 to +4.0 input / output voltage v t with respect to v ss ?0.5 note to v cc m, v cc s + 0.4 (4.0 v max.) v ambient operation temperature t a ?20 to +70 c storage temperature t stg ?55 to +125 c note ?1.0 v (min.) (pulse width 30 ns) caution exposing the device to stress above those listed in absolute maximum rating could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this specification. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions common parameter symbol condition min. typ. max. unit supply voltage v cc m, v cc s2.63.0v ambient operation temperature t a ?20 +70 c mobile specified ram parameter symbol condition min. typ. max. unit high level input voltage v ih v cc m x 0.8 v cc m + 0.3 v low level input voltage v il ? 0.3 note v cc m x 0.2 v note ?0.5 v (min.) (pulse width 30 ns) sram parameter symbol condition min. typ. max. unit high level input voltage v ih 2.4 v cc s + 0.4 v low level input voltage v il ? 0.3 note +0.5 v note ?0.5 v (min.) (pulse width 30 ns) capacitance (t a = 25 c, f = 1 mhz) parameter symbol test condition min. typ. max. unit input capacitance c in v in = 0 v tbd pf output capacitance c out v out = 0 v tbd pf remarks 1. v in : input voltage, v out : output voltage 2. these parameters are not 100% tested.
preliminary data sheet m15432ej1v0ds 10 mc-2311100 dc characteristics (recommended operating conditions unless otherwise noted) mobile specified ram parameter symbol test condition min. typ. max. unit input leakage current i li v in = 0 v to v cc m ?1.0 +1.0 a i/o leakage current i lo v i/o = 0 v to v cc m , /cem = v ih or ?1.0 +1.0 a /we = v il or /oe = v ih operating supply current i cca /cem = v il , minimum cycle time, i i/o = 0 ma 35 ma standby supply standby mode 1 i sb1 /cem v cc m ? 0.2 v, mode v cc m ? 0.2 v 100 a current standby mode 2 i sb2 /cem v cc m ? 0.2 v, mode 0.2 v 10 high level output voltage v oh i oh = ?0.5 ma v cc m 0.8 v low level output voltage v ol i ol = 1 ma v cc m 0.2 v sram parameter symbol test condition min. typ. max. unit input leakage current i li v in = 0 v to v cc s ?1.0 +1.0 a i/o leakage current i lo v i/o = 0 v to v cc s, /ce1s = v ih or ?1.0 +1.0 a ce2s = v il or /we = v il or /oe = v ih operating supply current i cca1 /ce1s = v il , ce2s = v ih ,?40ma i i/o = 0 ma, minimum cycle time i cca2 /ce1s = v il , ce2s = v ih ,?10 i i/o = 0 ma, cycle time = i cca3 /ce1s 0.2 v, ce2s v cc s ? 0.2 v, ? 8 i i/o = 0 ma, cycle time = 1 s v ih v cc s ? 0.2 v, v il 0.2 v standby supply current i sb /ce1s = v ih or ce2s = v il or /lb = /ub = v ih ?0.6ma i sb1 /ce1s v cc s ? 0.2 v, ce2s v cc s ? 0.2 v 0.5 7 a i sb2 ce2s 0.2 v 0.5 7 i sb3 /lb = /ub v cc s ? 0.2 v, /ce1s 0.2 v, 0.5 7 ce2s v cc s ? 0.2 v high level output voltage v oh i oh = ?0.5 ma 2.4 v low level output voltage v ol i ol = 1.0 ma 0.4 v remarks 1. v in : input voltage v i/o : input / output voltage 2. these dc characteristics are in common regardless products classification.
preliminary data sheet m15432ej1v0ds 11 mc-2311100 ac characteristics (recommended operating conditions unless otherwise noted) ac test conditions mobile specified ram input waveform (rise and fall time 5 ns) test points v cc m x 0.2 v v cc m x 0.8 v v cc m/2 v v cc m/2 v v cc m v ss 5 ns output waveform test points v cc m/2 v v cc m/2 v output load ac characteristics directed with the note should be measured with the output load shown in figure. c l : 50 pf 5 pf (t clz , t olz , t blz , t chz , t ohz , t bhz , t whz , t ow ) i/o (output) 50 ? 50 ? z o = c l v cc m/2 v
preliminary data sheet m15432ej1v0ds 12 mc-2311100 sram input waveform (rise and fall time 5 ns) test points v cc s x 0.1 v v cc s x 0.9 v v cc s/2 v v cc s/2 v output waveform test points v cc s/2 v v cc s/2 v output load 1 ttl + 50 pf
preliminary data sheet m15432ej1v0ds 13 mc-2311100 /cem, /ces timing parameter symbol test condition min. typ. max. unit note /cem, /ces recover time t ccr 0ns
preliminary data sheet m15432ej1v0ds 14 mc-2311100 read cycle (mobile specified ram) parameter symbol mc-2311100-b80 mc-2311100-b90 mc-2311100-b10 unit notes min. max. min. max. min. max. read cycle time t rc 80 10,000 90 10,000 110 10,000 ns 1 identical address read cycle time t rc1 80 10,000 90 10,000 110 10,000 ns 2 address skew time t skew 10 15 20 ns 3 /cem pulse width t cp 10 10 10 ns address access time t aa 80 90 100 ns 4 /cem access time t acs 80 90 100 ns /oe to output valid t oe 35 40 50 ns 5 /lb, /ub to output valid t ba 35 40 50 ns output hold from address change t oh 10 10 10 ns /cem to output in low impedance t clz 10 10 10 ns /oe to output in low impedance t olz 555ns /lb, /ub to output in low impedance t blz 555ns /cem to output in high impedance t chz 25 25 25 ns /oe to output in high impedance t ohz 25 25 25 ns /lb, /ub to output in high impedance t bhz 25 25 25 ns notes 1. one read cycle (t rc ) must satisfy the minimum value (t rc(min.) ) and maximum value (t rc(max.) = 10 s). t rc indicates the time from the /cem low level input point or address determination point, whichever is later, to the /cem high level input point or the next address change start point, whichever is earlier. as a result, there are the following four conditions for t rc . 1) time from address determination point to /cem high level input point (address access) 2) time from address determination point to next address change start point (address access) 3) time from /cem low level input point to next address change start point (/cem access) 4) time from /cem low level input point to /cem high level input point (/cem access) 2. the identical address read cycle time (t rc1 ) is the cycle time of one read operation when performing continuous read operations toggling /oe , /lb, and /ub with the address fixed and /cem low level. perform settings so that the sum (t rc ) of the identical address read cycle times (t rc1 ) is 10 s or less. 3. t skew indicates the following three types of time depending on the condition. 1) when switching /cem from high level to low level, t skew is the time from the /cem low level input point until the next address is determined. 2) when switching /cem from low level to high level, t skew is the time from the address change start point to the /cem high level input point. 3) when /cem is fixed to low level, t skew is the time from the address change start point until the next address is determined. since specs are defined for t skew only when /cem is active, t skew is not subject to limitations when /cem is switched from high level to low level following address determination, or when the address is changed after /cem is switched from low level to high level. 4. regarding t aa and t acs , only t aa is satisfied during address access (refer to 1) and 2) of note 1 ), and only t acs is satisfied during /cem access (refer to 3) of note 1 ). 5. regarding t ba and t oe , only t ba is satisfied if /oe becomes active later than /ub and /lb, and only t oe is satisfied if /ub and /lb become active before /oe.
preliminary data sheet m15432ej1v0ds 15 mc-2311100 write cycle (mobile specified ram) parameter symbol mc-2311100-b80 mc-2311100-b90 mc-2311100-b10 unit notes min. max. min. max. min. max. write cycle time t wc 80 10,000 90 10,000 110 10,000 ns 1 identical address write cycle time t wc1 80 10,000 90 10,000 110 10,000 ns 2 address skew time t skew 10 15 20 ns 3 /cem to end of write t cw 40 50 60 ns 4 /lb, /ub to end of write t bw 30 35 40 ns address valid to end of write t aw 35 45 55 ns write pulse width t wp 30 35 40 ns write recovery time t wr 20 20 20 ns 5 /cem pulse width t cp 10 10 10 ns address setup time t as 000ns byte write hold time t bwh 20 20 20 ns data valid to end of write t dw 20 25 30 ns data hold time t dh 000ns /oe to output in low impedance t olz 555ns /we to output in high impedance t whz 25 25 25 ns /oe to output in high impedance t ohz 25 25 25 ns output active from end of write t ow 555ns notes 1. one write cycle (t wc ) must satisfy the minimum value (t wc(min.) ) and the maximum value (t wc(max.) = 10 s). t wc indicates the time from the /cem low level input point or address determination point, whichever is after, to the /cem high level input point or the next address change start point, whichever is earlier. as a result, there are the following four conditions for t wc . 1) time from address determination point to /cem high level input point 2) time from address determination point to next address change start point 3) time from /cem low level input point to next address change start point 4) time from /cem low level input point to /cem high level input point 2. the identical address read cycle time (t wc1 ) is the cycle time of one write cycle when performing continuous write operations with the address fixed and /cem low level, changing /lb and /ub at the same time, and toggling /we, as well as when performing a continuous write toggling /lb and /ub. make settings so that the sum (t wc ) of the identical address write cycle times (t wc1 ) is 10 s or less. 3. t skew indicates the following three types of time depending on the condition. 1) when switching /cem from high level to low level, t skew is the time from the /cem low level input point until the next address is determined. 2) when switching /cem from low level to high level, t skew is the time from the address change start point to the /cem high level input point. 3) when /cem is fixed to low level, t skew is the time from the address change start point until the next address is determined. since specs are defined for t skew only when /cem is active, t skew is not subject to limitations when /cem is switched from high level to low level following address determination, or when the address is changed after /cem is switched from low level to high level.
preliminary data sheet m15432ej1v0ds 16 mc-2311100 4. definition of write start and write end /cem /we /lb, /ub status write start pattern 1 h to l l l if /we, /lb, /ub are low level, time when /cem changes from high level to low level write start pattern 2 l h to l l if /cem, /lb, /ub are low level, time when /we changes from high level to low level write start pattern 3 l l h to l if /cem, /we are low level, time when /lb or /ub changes from high level to low level write end pattern 1 l l to h l if /cem, /we, /lb, /ub are low level, time when /we changes from low level to high level write end pattern 2 l l l to h when /cem, /we, /lb, /ub are low level, time when /lb or /ub changes from low level to high level 5. definition of write end recovery time (t wr ) 1) time from write end to address change start point, or from write end to /cem high level input point 2) when /cem, /lb, /ub are low level and continuously written to the identical address, time from /we high level input point to /we low level input point 3) when /cem, /we are low level and continuously written to the identical address, time from /lb or /ub high level input point, whichever is later, to /lb or /ub low level input point, whichever is earlier. 4) when /cem is low level and continuously written to the identical address, time from write end to point at which /we , /lb, or /ub starts to change from high level to low level, whichever is earliest. read write cycle (mobile specified ram) parameter symbol mc-2311100-b80 mc-2311100-b90 mc-2311100-b10 unit notes min. max. min. max. min. max. read write cycle time t rwc 10,000 10,000 10,000 ns 1, 2 byte write setup time t bws 20 20 20 ns byte read setup time t brs 20 20 20 ns notes 1. make settings so that the sum (t rwc ) of the identical address read cycle time (t rc1 ) and the identical address write cycle time (t wc1 ) is 10 s or less when a write is performed at the identical address using /ub following a read using /lb with /cem low level, or when a write is performed using /lb following a read using /ub. 2. make settings so that the sum (t rwc ) of the identical address read cycle time (t rc1 ) and the identical address write cycle time (t wc1 ) is 10 s or less when a read is performed at the identical address using /ub following a write using /lb with /cem low level, or when a read is performed using /lb following a write using /ub.
preliminary data sheet m15432ej1v0ds 17 mc-2311100 read cycle (sram) parameter symbol mc-2311100-b80, b90, b10 unit notes min. max. read cycle time t rc 70 ns address access time t aa 70 ns 1 /ce1s access time t co1 70 ns ce2s access time t co2 70 ns /oe to output valid t oe 35 ns /lb, /ub to output valid t ba 70 ns output hold from address change t oh 10 ns /ce1s to output in low impedance t lz1 10 ns 2 ce2s to output in low impedance t lz2 10 ns /oe to output in low impedance t olz 0ns /lb, /ub to output in low impedance t blz 10 ns /ce1s to output in high impedance t hz1 25 ns ce2s to output in high impedance t hz2 25 ns /oe to output in high impedance t ohz 25 ns /lb, /ub to output in high impedance t bhz 25 ns notes 1. the output load is 1ttl + 50 pf. 2. the output load is 1ttl + 5 pf. write cycle (sram) parameter symbol mc-2311100-b80, b90, b10 unit note min. max. write cycle time t wc 70 ns /ce1s to end of write t cw1 55 ns ce2s to end of write t cw2 55 ns /lb, /ub to end of write t bw 55 ns address valid to end of write t aw 55 ns address setup time t as 0ns write pulse width t wp 50 ns write recovery time t wr 0ns data valid to end of write t dw 30 ns data hold time t dh 0ns /we to output in high impedance t whz 25 ns 1 output active from end of write t ow 5ns note 1. the output load is 1ttl + 50 pf.
preliminary data sheet m15432ej1v0ds 18 mc-2311100 low v cc data retention characteristics (t a = ? 20 to +70 c) parameter symbol test condition mc-2311100-b80, b90, b10 unit min. typ. max. data retention supply voltage v ccdr1 /ce1s v cc s ? 0.2 v,ce2s v cc s ? 0.2 v 1.0 3.6 v v ccdr2 ce2s 0.2 v 1.0 3.6 v ccdr3 /lb = /ub v cc s ? 0.2 v, 1.0 3.6 /ce1s 0.2 v, ce2s v cc s ? 0.2 v data retention supply current i ccdr1 v cc s = 1.5 v, /ce1s v cc s ? 0.2 v, 0.3 3.0 a ce2s v cc s ? 0.2 v or ce2s 0.2 v i ccdr2 v cc s = 1.5 v, ce2s 0.2 v 0.3 3.0 i ccdr3 v cc s = 1.5 v, /lb = /ub v cc s ? 0.2 v, 0.3 3.0 /ce1s 0.2 v, ce2s v cc s ? 0.2 v chip deselection to data retention mode t cdr 0ns operation recovery time t r t rc note ns note t rc : read cycle time
preliminary data sheet m15432ej1v0ds 19 mc-2311100 4. timing charts figure 4-1. alternating mobile specified ram to sram timing chart /cem (input) /ce1s (input) t ccr t ccr ce2s (input)
preliminary data sheet m15432ej1v0ds 20 mc-2311100 figure 4-2. read cycle timing chart 1 (mobile specified ram) t chz t oh t clz t acs hi-z t blz t ba t bhz t oe t skew t skew t cp t cp t rc t olz t ohz t chz t clz t aa hi-z t blz t ba t bhz t oe t skew t cp t cp t rc t olz t ohz t skew address (input) /cem (input) /oe (input) i/o (output) /lb, /ub (input) address (input) /cem (input) /oe (input) i/o (output) /lb, /ub (input) data out data out caution if the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the read cycle time (t rc ), none of the data can be guaranteed. remark in read cycle, /we should be fixed to high.
preliminary data sheet m15432ej1v0ds 21 mc-2311100 t aa t rc t skew t skew t rc t skew hi-z t aa t oe t olz t blz t oh t cp t rc t chz t acs t clz t bhz t ba t blz t skew t cp t rc t chz t acs t clz t bhz t ba t blz t bhz t chz t oh t aa t ohz t rc t clz t ba t oh address (input) /cem (input) /oe (input) i/o (output) /lb, /ub (input) data out data out data out data out data out caution if the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the read cycle time (t rc ), none of the data can be guaranteed. remark in read cycle, /we should be fixed to high. figure 4-3 read cycle timing chart 2 (mobile specified ram)
preliminary data sheet m15432ej1v0ds 22 mc-2311100 t aa t rc t skew t clz t rc t skew t rc t skew t rc t skew t rc t skew hi-z hi-z t blz t blz t olz t oe t ba t ba t oh t bhz t bhz t ohz t oh t oh t bhz t ohz t oh t bhz t ohz t aa t blz t olz t oe t ba t blz t olz t oe t ba t aa address (input) /cem (input) /oe (input) i/o0 - 7 (output) /lb (input) i/o8 - 15 (output) /ub (input) data out data out data out data out caution if the address is changed using a value that is either lower than the minimum value or higher than the maximum value f or the read cycle time (t rc ), none of the data can be guaranteed. remark in read cycle, /we should be fixed to high. figure 4-4. read cycle timing chart 3 (mobile specified ram)
preliminary data sheet m15432ej1v0ds 23 mc-2311100 figure 4-5. read cycle timing chart 4 (mobile specified ram) t skew t skew hi-z hi-z t rc1 t ba t ba t rc1 t rc t aa t oe t oe t olz t blz t olz t blz t ohz t bhz t ohz t bhz address (input) /cem (input) /oe (input) i/o (output) /lb, /ub (input) data out data out note note caution if the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the read cycle time (t rc ), none of the data can be guaranteed. note to perform a continuous read toggling /oe, /ub, and /lb with /cem low level at an identical address, make settings so that the sum (t rc ) of the identical address read cycle times (t rc1 ) is 10 s or less. remark in read cycle, /we should be fixed to high.
preliminary data sheet m15432ej1v0ds 24 mc-2311100 figure 4-6. write cycle timing chart 1 (mobile specified ram) t bw t dw t dh hi-z t wp t wr t skew t cp hi-z t wc t aw t skew t dw t dh t as t wp t wr t as t bw t wc t aw t bw t dw t dh hi-z t wp t wr t skew t cp hi-z t wc t skew t dw t dh t wp t wr t bw t wc t cw t cw t skew address (input) /cem (input) /we (input) i/o (intput) /lb, /ub (input) data in data in address (input) /cem (input) /we (input) i/o (intput) /lb, /ub (input) data in data in cautions 1. during address transition, at least one of pins /cem, /we should be inactivated. 2. do not input data to the i/o pins while they are in the output state. 3. if the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the write cycle time (t wc ), none of the data can be guaranteed. remark write operation is done during the overlap time of a low /cem, /we, /lb and/or /ub.
preliminary data sheet m15432ej1v0ds 25 mc-2311100 figure 4-7. write cycle timing chart 2 (mobile specified ram) t cw t aw t as t wp t skew t wc t skew t aw t dw t dh t wr t ow t aw t skew t cp t whz hi-z hi-z hi-z hi-z hi-z t ohz t olz t wc t wc t wp t wp t wr t wr t dw t dh t dw t dh t skew t dw t dh t skew t skew hi-z hi-z hi-z t wc1 t as t wp t wp t wr t dw t dh t wc1 t bw t skew t wc t wr address (input) /cem (input) /we (input) i/o (intput / output) /oe (input) address (input) /cem (input) /we (input) i/o (intput) /lb, /ub (input) data in indefinite data out data in data in data in data in note note cautions 1. during address transition, at least one of pins /cem, /we should be inactivated. 2. do not input data to the i/o pins while they are in the output state. 3. if the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the write cycle time (t wc ), none of the data can be guaranteed. note if /lb and /ub are changed at the same time with /cem low level and a continuous write operation toggling /we is performed, make settings so that the sum (t wc ) of the identical address write cycle time (t wc1 ) is 10 s or less. remarks 1. write operation is done during the overlap time of a low /cem, /we, /lb and/or /ub. 2. when /we is at low, the i/o pins are always high impedance. when /we is at high, read operation is executed. therefore /oe should be at high to make the i/o pins high impedance.
preliminary data sheet m15432ej1v0ds 26 mc-2311100 figure 4-8. write cycle timing chart 3 (/cem controlled) (mobile specified ram) t as t cw t wr t wc t dw t dh hi-z hi-z hi-z t wc t dw t dh t cw t wr t as t as t cw t wr t wc t dw t dh hi-z hi-z hi-z t wc t dw t dh t cw t wr t as address (input) /cem (input) /we (input) i/o (intput) /lb, /ub (input) data in data in address (input) /cem (input) /we (input) i/o (intput) /lb, /ub (input) data in data in cautions 1. during address transition, at least one of pins /cem, /we should be inactivated. 2. do not input data to the i/o pins while they are in the output state. 3. if the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the write cycle time (t wc ), none of the data can be guaranteed. remark write operation is done during the overlap time of a low /cem, /we, /lb and/or /ub.
preliminary data sheet m15432ej1v0ds 27 mc-2311100 figure 4-9. write cycle timing chart 4 (/lb, /ub controlled 1) (mobile specified ram) t bw t dw t dh hi-z t wp t wr t skew hi-z t wc t aw t skew t dw t dh t as t wc t aw t bw t as t wr t bw t dw t dh hi-z t wp t wr t skew hi-z t wc t cw t skew t dw t dh t as t wc t bw t as t wr t aw address (input) /cem (input) /we (input) i/o (intput) /lb, /ub (input) data in data in address (input) /cem (input) /we (input) i/o (intput) /lb, /ub (input) data in data in cautions 1. during address transition, at least one of pins /cem, /we should be inactivated. 2. do not input data to the i/o pins while they are in the output state. 3. if the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the write cycle time (t wc ), none of the data can be guaranteed. remark write operation is done during the overlap time of a low /cem, /we, /lb and/or /ub.
preliminary data sheet m15432ej1v0ds 28 mc-2311100 figure 4-10. write cycle timing chart 5 (/lb, /ub controlled 2) (mobile specified ram) t dw t dh t skew t skew hi-z hi-z hi-z t wc1 t as t bw t bw t wr t dw t dh t wc1 t wr t wc t wp data in data in address (input) /cem (input) /we (input) i/o (intput) /lb, /ub (input) note note cautions 1. during address transition, at least one of pins /cem, /we should be inactivated. 2. do not input data to the i/o pins while they are in the output state. 3. if the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the write cycle time (t wc ), none of the data can be guaranteed. note if /lb and /ub are changed at the same time with /cem low level and a continuous write operation toggling /we is performed, make settings so that the sum (t wc ) of the identical address write cycle time (t wc1 ) is 10 s or less. remark write operation is done during the overlap time of a low /cem, /we, /lb and/or /ub.
preliminary data sheet m15432ej1v0ds 29 mc-2311100 figure 4-11. write cycle timing chart 6 (/lb, /ub independent controlled 1) (mobile specified ram) t wp t as t cw t wr t wc1 t bw hi-z hi-z t bw t wc1 t dw t dh t wr hi-z hi-z t dw t dh t wc address (input) /cem (input) /we (input) i/o0 - 7 (intput) /lb (input) i/o8 - 15 (intput) /ub (input) data in data in note note cautions 1. during address transition, at least one of pins /cem, /we should be inactivated. 2. do not input data to the i/o pins while they are in the output state. 3. if the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the write cycle time (t wc ), none of the data can be guaranteed. note if /lb and /ub are changed at the same time with /cem low level and a continuous write operation toggling /we is performed, make settings so that the sum (t wc ) of the identical address write cycle time (t wc1 ) is 10 s or less. remark write operation is done during the overlap time of a low /cem, /we, /lb and/or /ub.
preliminary data sheet m15432ej1v0ds 30 mc-2311100 figure 4-12. write cycle timing chart 7 (/lb, /ub independent controlled 2) (mobile specified ram) t wp t as t cw t wc t bw hi-z hi-z t bw t dw t dh hi-z hi-z t dw t dh t wr t wr t as t bwh t cw t wp address (input) /cem (input) /we (input) i/o0 - 7 (intput) /lb (input) i/o8 - 15 (intput) /ub (input) data in data in cautions 1. during address transition, at least one of pins /cem, /we should be inactivated. 2. do not input data to the i/o pins while they are in the output state. 3. if the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the write cycle time (t wc ), none of the data can be guaranteed. remark write operation is done during the overlap time of a low /cem, /we, /lb and/or /ub.
preliminary data sheet m15432ej1v0ds 31 mc-2311100 figure 4-13. read write cycle timing chart 1 (/lb, /ub independent controlled 1) (mobile specified ram) t wp t bws t rc1 hi-z hi-z t bw t wc1 t wr hi-z hi-z t dw t dh t rwc t clz t blz t bhz t acs t aa address (input) /cem (input) /we (input) i/o0 - 7 (output) /lb (input) i/o8 - 15 (intput) /ub (input) data out data in note note cautions 1. during address transition, at least one of pins /cem, /we should be inactivated. 2. do not input data to the i/o pins while they are in the output state. 3. if the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the identical address read cycle time (t rc1 ) and the identical address write cycle time (t wc1 ), none of the data can be guaranteed. note make settings so that the sum (t rwc ) of the identical address read cycle time (t rc1 ) and the identical address write cycle time (t wc1 ) is 10 s or less when a write is performed at the identical address using /ub following a read using /lb with /cem low level, or when a write is performed using /lb following a read using /ub. remark write operation is done during the overlap time of a low /cem, /we, /lb and/or /ub.
preliminary data sheet m15432ej1v0ds 32 mc-2311100 figure 4-14. read write cycle timing chart 2 (/lb, /ub independent controlled 2) (mobile specified ram) t wp t rc1 hi-z hi-z t bw t wc1 t wr hi-z hi-z t dw t dh t rwc t blz t bhz t brs t ba t cw t as address (input) /cem (input) /we (input) i/o0 - 7 (input) /lb (input) i/o8 - 15 (output) /ub (input) data in data out note note cautions 1. during address transition, at least one of pins /cem, /we should be inactivated. 2. do not input data to the i/o pins while they are in the output state. 3. if the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the identical address read cycle time (t rc1 ) and the identical address write cycle time (t wc1 ), none of the data can be guaranteed. note make settings so that the sum (t rwc ) of the identical address read cycle time (t rc1 ) and the identical address write cycle time (t wc1 ) is 10 s or less when a write is performed at the identical address using /ub following a read using /lb with /cem low level, or when a write is performed using /lb following a read using /ub. remark write operation is done during the overlap time of a low /cem, /we, /lb and/or /ub.
preliminary data sheet m15432ej1v0ds 33 mc-2311100 figure 4-15. read write cycle timing chart 3 (/lb, /ub independent controlled 3) (mobile specified ram) address (input) /cem (input) /we (input) i/o0 - 7 (input) /lb (input) i/o8 - 15 (output) /ub (input) t bw t rc1 hi-z hi-z t wp t wc1 t wr hi-z hi-z t dw t dh t rwc t blz t bhz t ba t cw t as data in data out note note cautions 1. during address transition, at least one of pins /cem, /we should be inactivated. 2. do not input data to the i/o pins while they are in the output state. 3. if the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the identical address read cycle time (t rc1 ) and the identical address write cycle time (t wc1 ), none of the data can be guaranteed. note make settings so that the sum (t rwc ) of the identical address read cycle time (t rc1 ) and the identical address write cycle time (t wc1 ) is 10 s or less when a write is performed at the identical address using /ub following a read using /lb with /cem low level, or when a write is performed using /lb following a read using /ub. remark write operation is done during the overlap time of a low /cem, /we, /lb and/or /ub.
preliminary data sheet m15432ej1v0ds 34 mc-2311100 figure 4-16. standby mode 2 entry and recovery timing chart (mobile specified ram) address (input) /cem (input) mode (input) t cm t rc t cp standby mode 2 wait time 200 s read operation 8 times normal operation parameter symbol min. max. unit note /cem high to mode low t cm 0ns cautions 1. make mode and /cem high level during the wait time. 2. make mode high level during the wait time and eight read operations. 3. the read operation must satisfy the specs described on page 34 (read cycle (mobile specified ram)). 4. the read operation address can be either v ih or v il . 5. perform reading by toggling /cem. 6. to prevent bus contention, it is recommended to set /oe to high level. however, do not input data to the i/o pins if /oe is low level during a read operation.
preliminary data sheet m15432ej1v0ds 35 mc-2311100 figure 4-17. read cycle timing chart (sram) t hz2 t rc t oh t hz1 t blz t ba t lz2 t co2 t lz1 t co1 t bhz t aa high impedance data out /lb, /ub (input) ce2s (input) /ce1s (input) address (input) i/o (output) t olz t oe t ohz /oe (input) remark in read cycle, /we should be fixed to high level.
preliminary data sheet m15432ej1v0ds 36 mc-2311100 figure 4-18. write cycle timing chart 1 (/we controlled) (sram) t wc t cw1 t bw t whz t dw t dh t ow indefinite data out high impe- dance high impe- dance data in indefinite data out address (input) /ce1 (input) /lb, /ub (input) i/o (input / output) ce2 (input) t cw2 t aw t wp t as t wr /we (input) cautions 1. during address transition, at least one of pins /ce1s, ce2s, /we should be inactivated. 2. do not input data to the i/o pins while they are in the output state. remarks 1. write operation is done during the overlap time of a low level /ce1s, /we, /lb and/or /ub, and a high level ce2s. 2. if /ce1s changes to low level at the same time or after the change of /we to low level, or if ce2s changes to high level at the same time or after the change of /we to low level, the i/o pins will remain high impedance state. 3. when /we is at low level, the i/o pins are always high impedance. when /we is at high level, read operation is executed. therefore /oe should be at high level to make the i/o pins high impedance.
preliminary data sheet m15432ej1v0ds 37 mc-2311100 figure 4-19. write cycle timing chart 2 (/ce1s controlled) (sram) t wc t as t cw1 t dw t dh data in high impedance address (input) /ce1s (input) /lb, /ub (input) i/o (input) high impedance ce2s (input) t cw2 t aw t wp t wr /we (input) t bw cautions 1. during address transition, at least one of pins /ce1s, ce2s, /we should be inactivated. 2. do not input data to the i/o pins while they are in the output state. remark write operation is done during the overlap time of a low level /ce1s, /we, /lb and/or /ub, and a high level ce2s.
preliminary data sheet m15432ej1v0ds 38 mc-2311100 figure 4-20. write cycle timing chart 3 (ce2s controlled) (sram) t wc t as t cw2 t bw t dw t dh data in high impedance address (input) ce2s (input) /lb, /ub (input) i/o (input) high impedance /ce1s (input) t cw1 t aw t wp t wr /we (input) cautions 1. during address transition, at least one of pins /ce1s, ce2s, /we should be inactivated. 2. do not input data to the i/o pins while they are in the output state. remark write operation is done during the overlap time of a low level /ce1s, /we, /lb and/or /ub, and a high level ce2s.
preliminary data sheet m15432ej1v0ds 39 mc-2311100 figure 4-21. write cycle timing chart 4 (/lb, /ub controlled) (sram) t wc t dw t dh data in high impedance address (input) /lb, /ub (input) i/o (input) high impedance ce2s (input) t cw2 t aw t wp t wr /we (input) t as t bw /ce1s (input) t cw1 cautions 1. during address transition, at least one of pins /ce1s, ce2s, /we should be inactivated. 2. do not input data to the i/o pins while they are in the output state. remark write operation is done during the overlap time of a low level /ce1s, /we, /lb and/or /ub, and a high level ce2s.
preliminary data sheet m15432ej1v0ds 40 mc-2311100 figure 4-22. data retention timing chart 1 (/ce1s controlled) (sram) v ih (min.) v ccdr (min.) v il (max.) v cc s v ss /ce1 /ce1 v cc s ? 0.2 v v cc (min.) t cdr data retention mode t r remark on the data retention mode by controlling /ce1s, the input level of ce2s must be v cc ? 0.2 v or 0.2 v. the other pins (address, i/o, /we, /oe, /lb, /ub) can be in high impedance state. figure 4-23. data retention timing chart 2 (ce2s controlled) (sram) v ih (min.) v ccdr (min.) v il (max.) v cc s v ss ce2 ce2 0.2 v v cc (min.) t cdr data retention mode t r remark on the data retention mode by controlling ce2s, the other pins (/ce1s, address, i/o, /we, /oe, /lb, /ub) can be in high impedance state.
preliminary data sheet m15432ej1v0ds 41 mc-2311100 figure 4-24. data retention timing chart 3 (/lb, /ub controlled) (sram) t cdr data retention mode v ih (min.) v ccdr (min.) v il (max.) t r v cc s v ss /lb, /ub /lb, /ub v cc s ? 0.2 v v cc (min.) remark on the data retention mode by controlling /lb and /ub, the input level of /ce1s and ce2s must be v cc ? 0.2 v or 0.2 v. the other pins (address, i/o, /we, /oe) can be in high impedance state.
preliminary data sheet m15432ej1v0ds 42 mc-2311100 5. package drawing 61-pin tape fbga (9x7) s x e ab m s wb w sa s y item millimeters d 9.0 0.1 7.0 0.1 e 0.2 b 0.45 0.05 x 0.08 y 0.1 y1 0.1 zd 0.7 ze 0.8 w a 1.1 0.1 a1 0.26 0.05 a2 0.84 b ? index mark a 0.8 e a1 a2 s s y1 a b zd ze kjhgfedcba 8 7 6 5 4 3 2 1 d e
preliminary data sheet m15432ej1v0ds 43 mc-2311100 6. recommended soldering conditions please consult with our sales offices for soldering conditions of the mc-2311100. types of surface mount device mc-2311100f9-b80-bq1 : 61-pin tape fbga (9 7) MC-2311100F9-B90-BQ1 : 61-pin tape fbga (9 7) mc-2311100f9-b10-bq1 : 61-pin tape fbga (9 7)
preliminary data sheet m15432ej1v0ds 44 mc-2311100 [memo]
preliminary data sheet m15432ej1v0ds 45 mc-2311100 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
mc-2311100 m8e 00. 4 the information in this document is current as of november, 2001. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above). ? ? ? ? ? ?

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